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| Order this document by MC34129/D High Performance Current Mode Controllers The MC34129/MC33129 are high performance current mode switching regulators specifically designed for use in low power digital telephone applications. These integrated circuits feature a unique internal fault timer that provides automatic restart for overload recovery. For enhanced system efficiency, a start/run comparator is included to implement bootstrapped operation of VCC. Other functions contained are a temperature compensated reference, reference amplifier, fully accessible error amplifier, sawtooth oscillator with sync input, pulse width modulator comparator, and a high current totem pole driver ideally suited for driving a power MOSFET. Also included are protective features consisting of soft-start, undervoltage lockout, cycle-by-cycle current limiting, adjustable deadtime, and a latch for single pulse metering. Although these devices are primarily intended for use in digital telephone systems, they can be used cost effectively in many other applications. * Current Mode Operation to 300 kHz MC34129 MC33129 HIGH PERFORMANCE CURRENT MODE CONTROLLERS SEMICONDUCTOR TECHNICAL DATA 14 1 P SUFFIX PLASTIC PACKAGE CASE 646 * * * * * * * * * Automatic Feed Forward Compensation Latching PWM for Cycle-by-Cycle Current Limiting Continuous Retry after Fault Timeout Soft-Start with Maximum Peak Switch Current Clamp Internally Trimmed 2% Bandgap Reference High Current Totem Pole Driver Input Undervoltage Lockout Low Startup and Operating Current Direct Interface with Motorola SENSEFET Products Drive Output Drive Ground Ramp Input 14 1 D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14) PIN CONNECTIONS 1 2 3 14 VCC 13 Start/Run Output 12 CSoft-Start Feedback/ 11 PWM Input Error Amp 10 Inverting Input 9 Error Amp Noninverting Input 8 Vref 1.25 V (Top View) Simplified Block Diagram Start/Run 12 Soft-Start and Fault Timer Undervoltage Lockout 1.25V Reference Gnd 7 Error Amp 6 X2 Latching PWM RT/CT Sync/Inhibit Input 5 4 Oscillator 9 Noninverting Input + 10 - Inverting Input 11 Feedback/ 1 PWM Input Drive Out 2 Drive Gnd 3 Ramp Input 13 Start/Run Output VCC Sync/Inhibit 4 Input RT/CT 5 Vref 2.5 V 6 CSoft-Start 14 Gnd 7 8 Vref 1.25V ORDERING INFORMATION Device MC34129D MC34129P MC33129D MC33129P Operating Temperature Range TA = 0 to +70C TA = - 40 to +85C Package SO-14 Plastic DIP SO-14 Plastic DIP Rev 1 Vref 2.5V (c) Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA 1 MC34129 MC33129 MAXIMUM RATINGS Rating VCC Zener Current Start/Run Output Zener Current Analog Inputs (Pins 3, 5, 9, 10, 11, 12) Sync Input Voltage Drive Output Current, Source or Sink Current, Reference Outputs (Pins 6, 8) Power Dissipation and Thermal Characteristics D Suffix, Plastic Package Case 751A Maximum Power Dissipation @ TA = 70C Thermal Resistance, Junction-to-Air P Suffix, Plastic Package Case 646 Maximum Power Dissipation @ TA = 70C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature MC34129 MC33129 Storage Temperature Range Symbol IZ(VCC) IZ(Start/Run) - Vsync IDRV Iref Value 50 50 -0.3 to 5.5 -0.3 to VCC 1.0 20 Unit mA mA V V A mA PD RJA PD RJA TJ TA 552 145 800 100 +150 0 to +70 -40 to +85 mW C/W mW C/W C C Tstg -65 to +150 C ELECTRICAL CHARACTERISTICS (VCC = 10 V, TA = 25C [Note 1], unless otherwise noted.) Characteristics REFERENCE SECTIONS Reference Output Voltage, TA = 25C 1.25 V Ref., IL = 0 mA 2.50 V Ref., IL = 1.0 mA Reference Output Voltage, TA = Tlow to Thigh 1.25 V Ref., IL = 0 mA 2.50 V Ref., IL = 1.0 mA Line Regulation (VCC = 4.0 V to 12 V) 1.25 V Ref., IL = 0 mA 2.50 V Ref., IL = 1.0 mA Load Regulation 1.25 V Ref., IL = -10 A to +500 A 2.50 V Ref., IL = -0.1 mA to +1.0 mA ERROR AMPLIFIER Input Offset Voltage (Vin = 1.25 V) TA = 25C TA = Tlow to Thigh Input Offset Current (Vin = 1.25 V) Input Bias Current (Vin = 1.25 V) TA = 25C TA = Tlow to Thigh Input Common Mode Voltage Range Open Loop Voltage Gain (VO = 1.25 V) Gain Bandwidth Product (VO = 1.25 V, f = 100 kHz) Power Supply Rejection Ratio (VCC = 5.0 V to 10 V) Output Source Current (VO = 1.5 V) Output Voltage Swing High State (ISource = 0 A) Low State (ISink = 500 A) NOTE: 1. Tlow = 0C for MC34129 -40C for MC33129 Thigh = +70C for MC34129 +85C for MC33129 Symbol Min Typ Max Unit Vref 1.225 2.375 Vref 1.200 2.250 Regline - - Regload - - 1.0 3.0 12 25 2.0 10 12 50 - - 1.300 2.750 1.250 2.500 1.275 2.625 V V mV mV VIO - - IIO IIB - - VICR AVOL GBW PSRR ISource VOH VOL - 65 500 65 40 1.75 - 25 - 0.5 to 5.5 87 750 85 80 1.96 0.1 - 200 - - - - - 2.25 0.15 - 1.5 - 10 - 10 - mV nA nA V dB kHz dB A V 2 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 ELECTRICAL CHARACTERISTICS (VCC = 10 V, TA = 25C [Note 1], unless otherwise noted.) Characteristics PWM COMPARATOR Input Offset Voltage (Vin = 1.25 V) Input Bias Current Propagation Delay, Ramp Input to Drive Output SOFT-START Capacitor Charge Current (Pin 12 = 0 V) Buffer Input Offset Voltage (Vin = 1.25 V) Buffer Output Voltage (ISink = 100 A) FAULT TIMER Restart Delay Time START/RUN COMPARATOR Threshold Voltage (Pin 12) Threshold Hysteresis Voltage (Pin 12) Output Voltage (ISink = 500 A) Output Off-State Leakage Current (VOH = 15 V) Output Zener Voltage (IZ = 10 mA) OSCILLATOR Frequency (RT = 25.5 k, CT = 390 pF) Capacitor CT Discharge Current (Pin 5 = 1.2 V) Sync Input Current High State (Vin = 2.0 V) Low State (Vin = 0.8 V) Sync Input Resistance DRIVE OUTPUT Output Voltage High State (ISource = 200 mA) Low State (ISource = 200 mA) Low State Holding Current Output Voltage Rise Time (CL = 500 pF) Output Voltage Fall Time (CL = 500 pF) Output Pull-Down Resistance UNDERVOLTAGE LOCKOUT Startup Threshold Hysteresis TOTAL DEVICE Power Supply Current RT = 25.5 k, CT = 390 pF, CL = 500 pF Power Supply Zener Voltage (IZ = 10 mA) NOTE: 1. Tlow = 0C for MC34129 -40C for MC33129 Thigh = +70C for MC34129 +85C for MC33129 Symbol Min Typ Max Unit VIO IIB tPLH(IN/DRV) 150 - - 275 -120 250 400 -250 - mV A ns A mV V s Ichg VIO VOL 0.75 - - 1.2 15 0.15 1.50 40 0.225 tDLY 200 400 600 Vth VH VOL IS/R(leak) VZ - - 9.0 - - 2.0 350 10 0.4 (VCC + 7.6) - - 10.3 2.0 - V mV V A V fOSC Idischg IIH IIL Rin 80 240 - - 12.5 100 350 40 15 32 120 460 125 35 50 kHz A A k V VOH VOL IH tr tf RPD 8.3 - - - - 100 8.9 1.4 225 390 30 225 - 1.8 - - - 350 A ns ns k Vth VH 3.0 5.0 3.6 10 4.2 15 V % ICC VZ 1.0 12 2.5 14.3 4.0 - mA V MOTOROLA ANALOG IC DEVICE DATA 3 MC34129 MC33129 Figure 1. Timing Resistor versus Oscillator Frequency 1.0 M R T , TIMING RESISTOR ( ) 500 k 200 k 100 k 50 k 20 k 10 k 5.0 CT = 5.0 nF 2.0 nF 1.0 nF 500 pF 200 pF 100pF Figure 2. Output Deadtime versus Oscillator Frequency 100 %DT, PERCENT OUTPUT DEAD-TIME 2.0 nF 1.0 nF 500 pF 200 pF 100 pF VCC = 10 V TA = 25C 50 CT = 5.0 nF 20 5.0 2.0 1.0 5.0 10 VCC = 10 V TA = 25C 20 50 100 200 fOSC, OSCILLATOR FREQUENCY (kHz) 500 10 20 50 100 200 fOSC, OSCILLATOR FREQUENCY (kHz) 500 f OSC, OSCILLATOR FREQUENCY CHANGE (%) Figure 3. Oscillator Frequency Change versus Temperature A VOL , OPEN LOOP VOLTAGE GAIN (dB) 60 8.0 VCC = 10 V RT = 25.5 k CT = 390 pF Figure 4. Error Amp Open Loop Gain and Phase versus Frequency 0 EXCESS PHASE (DEGREES) , 200 mV/DIV 1.0 s/DIV VCC = 10 V VO = 1.25 V RL = TA = 25C 40 4.0 0 -4.0 -8.0 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 Gain Phase 45 20 90 0 135 -20 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M 180 10 M Figure 5. Error Amp Small-Signal Transient Response TA = 25C 1.05 V 1.5 V Figure 6. Error Amp Large-Signal Transient Response TA = 25C 1.0 V 20 mV/DIV 1.0 V 0.95 V 0.5 V 0.5 s/DIV 4 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 Figure 7. Error Amp Open Loop DC Gain versus Load Resistance V sat , OUTPUT SATURATION VOLTAGE (V) A VOL, OPEN LOOP VOLTAGE GAIN (dB) 90 1.0 VCC = 10 V Pins 8 to 9, 6 to 10 Pins 2, 5, 7 to Gnd TA = 25C Figure 8. Error Amp Output Saturation versus Sink Current 80 0.8 0.6 0.4 0.2 0 0 70 60 50 0 VCC = 10 V VO = 1.25 V RL to 1.25 Vref TA = 25C 20 40 60 80 RL, OUTPUT LOAD RESISTANCE (k) 100 2.0 4.0 6.0 ISink, OUTPUT SINK CURRENT (mA) 8.0 Figure 9. Soft-Start Buffer Output Saturation versus Sink Current V sat , OUTPUT SATURATION VOLTAGE (V) V ref , REFERENCE OUTPUT VOLTAGE (V) 1.0 VCC = 10 V Pins 8 to 9 Pins 2, 5, 7, 10, 12 to Gnd TA = 25C 3.2 Figure 10. Reference Output Voltage versus Supply Voltage TA = 25C 2.4 Vref 2.5 V, RL = 2.5 k 0.8 0.6 0.4 0.2 0 1.6 Vref 1.25 V, RL = 0.8 0 100 200 300 400 500 0 0 4.0 8.0 VCC, SUPPLY VOLTAGE (V) 12 16 ISink, OUTPUT SINK CURRENT (A) 0 VCC = 10 V -4.0 -8.0 -12 -16 -20 -24 0 2.0 4.0 6.0 8.0 10 +25C TA = - 40C +85C V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV) V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV) Figure 11. 1.25 V Reference Output Voltage Change versus Source Current Figure 12. 2.5 V Reference Output Voltage Change versus Source Current 0 VCC = 10 V -4.0 -8.0 -12 -16 -20 -24 0 0.4 0.8 1.2 1.6 2.0 TA = - 40C 25C 85C Iref, REFERENCE OUTPUT SOURCE CURRENT (mA) Iref, REFERENCE OUTPUT SOURCE CURRENT (mA) MOTOROLA ANALOG IC DEVICE DATA 5 MC34129 MC33129 V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV) V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV) Figure 13. 1.25 V Reference Output Voltage versus Temperature 0 -2.0 -4.0 -6.0 -8.0 -10 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 VCC = 10 V RL = *Vref at TA = 25C *Vref = 1.225 V *Vref = 1.250 V *Vref = 1.275 V Figure 14. 2.5 V Reference Output Voltage versus Temperature 0 4.0 8.0 -12 -16 -20 -55 -25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125 *Vref = 2.375 V *Vref = 2.500 V *Vref = 2.625 V VCC = 10 V RL = 2.5 k *Vref at TA = 25C Figure 15. Drive Output Saturation versus Load Current V sat , OUTPUT SATURATION VOLTAGE (V) 0 VCC -1.0 -2.0 -3.0 3.0 2.0 1.0 Gnd 0 0 200 400 600 800 0 Sink Saturation (Load to VCC) Source Saturation (Load to Ground) VCC = 10 V TA = 25C 10 Figure 16. Drive Output Waveform RL = CL = 500 pF TA = 25C 2.0 V/DIV 1.0 s/DIV R IO, OUTPUT LOAD CURRENT (mA) Figure 17. Supply Current versus Supply Voltage 10 I CC , SUPPLY CURRENT (mA) RT = 25.5 k CT = 390 pF TA = 25C 8.0 6.0 4.0 2.0 0 CL = 500 pF CL = 15 pF 0 4.0 8.0 VCC, SUPPLY VOLTAGE (V) 12 16 6 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 PIN FUNCTION DESCRIPTION Pin 1 2 3 4 Function Drive Output Drive Ground Ramp Input Sync/Inhibit Input Description This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sinked by this pin. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. A voltage proportional to the inductor current is connected to this input. The PWM uses this information to terminate output switch conduction. A rectangular waveform applied to this input will synchronize the Oscillator and limit the maximum Drive Output duty cycle. A dc voltage within the range of 2.0 V to VCC will inhibit the controller. The free-running Oscillator frequency and maximum Drive Output duty cycle are programmed by connecting resistor RT to Vref 2.5 V and capacitor CT to Ground. Operation to 300 kHz is possible. This output is derived from Vref 1.25 V. It provides charging current for capacitor CT through resistor RT. This pin is the control circuitry ground return and is connected back to the source ground. This output furnishes a voltage reference for the Error Amplifier noninverting input. This is the noninverting input of the Error Amplifier. It is normally connected to the 1.25 V reference. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. This pin is available for loop compensation. It is connected to the Error Amplifier and Soft-Start Buffer outputs, and the Pulse Width Modulator input. A capacitor CSoft-Start is connected from this pin to Ground for a controlled ramp-up of peak inductor current during startup. This output controls the state of an external bootstrap transistor. During the start mode, operating bias is supplied by the transistor from Vin. In the run mode, the transistor is switched off and bias is supplied by an auxiliary power transformer winding. This pin is the positive supply of the control IC. The controller is functional over a minimum VCC range of 4.2 V to 12 V. 5 RT/CT 6 7 8 9 10 11 12 13 Vref 2.50 V Ground Vref 1.25 V Error Amp Noninverting Input Error Amp Inverting Input Feedback/PWM Input CSoft-Start Start/Run Output 14 VCC MOTOROLA ANALOG IC DEVICE DATA 7 MC34129 MC33129 OPERATING DESCRIPTION The MC34129 series are high performance current mode switching regulator controllers specifically designed for use in low power telecommunication applications. Implementation will allow remote digital telephones and terminals to shed their power cords and derive operating power directly from the twisted pair used for data transmission. Although these devices are primarily intended for use in digital telephone systems, they can be used cost effectively in a wide range of converter applications. A representative block diagram is shown in Figure 18. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 2.5 V reference through resistor RT to approximately 1.25 V and discharged by an internal current sink to ground. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the lower input of the NOR gate high. This causes the Drive Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows Oscillator Frequency versus RT and Figure 2 Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a give frequency. In many noise sensitive applications it may be desirable to frequency-lock one or more switching regulators to an external system clock. This can be accomplished by applying the clock signal to the Synch/Inhibit Input. For reliable locking, the free-running oscillator frequency should be about 10% less than the clock frequency. Referring to the timing diagram shown Figure 19, the rising edge of the clock signal applied to the Sync/Inhibit Input, terminates charging of CT and Drive Output conduction. By tailoring the clock waveform, accurate duty cycle clamping of the Drive Output can be achieved. A circuit method is shown in Figure 20. The Sync/Inhibit Input may also be used as a means for system shutdown by applying a dc voltage that is within the range of 2.0 V to VCC. PWM Comparator and Latch The MC34129 operates as a current mode controller whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches a threshold level established by the output of the Error Amp or Soft-Start Buffer (Pin 11). Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The PWM Comparator-Latch configuration used, ensures that only a single pulse appears at the Drive Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground-referenced resistor RS in series with the source of output switch Q1. The Ramp Input adds an offset of 275 mV to this voltage to guarantee that no pulses appear at the Drive Output when Pin 11 is at its lowest state. This occurs at the beginning of the soft-start interval or when the power supply is operating and the load is removed. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 11 where: Ipk = V(Pin 11) - 0.275 V RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the voltage at Pin 11 will be internally clamped to 1.95 V by the output of the Soft-Start Buffer. Therefore the maximum peak switch current is: Ipk(max) = 1.95 V - 0.275 1.675 V = RS RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method which adjusts this voltage in discrete increments is shown in Figure 22. This method is possible because the Ramp Input bias current is always negative (typically -120 A). A positive temperature coefficient equal to that of the diode string will be exhibited by Ipk(max). An adjustable method that is more precise and temperature stable is shown in Figure 23. Erratic operation due to noise pickup can result if there is an excessive reduction of the clamp voltage. In this situation, high frequency circuit layout techniques are imperative. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Ramp Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 25. Error Amp and Soft-Start Buffer A fully-compensated Error Amplifier with access to both inputs and output is provided for maximum design flexibility. The Error Amplifier output is common with that of the Soft-Start Buffer. These outputs are open-collector (sink only) and are ORed together at the inverting input of the PWM Comparator. With this configuration, the amplifier that demands lower peak inductor current dominates control of the loop. Soft-Start is mandatory for stable startup when power is provided through a high source impedance such as the long twisted pair used in telecommunications. It effectively removes the load from the output of the switching power supply upon initial startup. The Soft-Start Buffer is configured as a unity gain follower with the noninverting input connected to Pin 12. An internal 1.0 A current source charges the soft-start capacitor (CSoft-Start) to an internally clamped level of 1.95 V. The rate of change of peak inductor current, during startup, is programmed by the capacitor value selected. Either the Fault Timer or the Undervoltage Lockout can discharge the soft-start capacitor. 8 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 Figure 18. Representative Block Diagram + - Start/Run Output Start/Run Comparator Undervoltage Lockout VCC 35k CSoft-Start 1.95V 7 PWM Comparator + - + 2.5V Reference 6 R RT 5 Oscillator CT 4 Sync/Inhibit Input 32k 3 Ramp Input RS S R Latch R 225k Q + - 1.25V 275mV + - Soft-Start Buffer + - VCC 80A 1.25V Reference VCC 3.6V + 14.3V 8 13 7.0V 14 VCC Vin = 20V + VCC 12 1.0A Fault Timer 1.95V Error Amp 9 Noninverting Input 10 Inverting Input Feedback/PWM 11 Input Q1 1 Drive Output 2 Drive Gnd + - Sink Only = Positive True Logic Figure 19. Timing Diagram 600 s Delay Sync/Inhibit Input Capacitor CT Latch "Set" Input Feedback/PWM Input Ramp Input Latch "Reset" Input Drive Output Start/Run Output 20 V 14.3 V MOTOROLA ANALOG IC DEVICE DATA 9 MC34129 MC33129 Fault Timer This unique circuit prevents sustained operating in a lockout condition. This can occur with conventional switching control ICs when operating from a power source with a high series impedance. If the power required by the load is greater than that available from the source, the input voltage will collapse, causing the lockout condition. The Fault Timer provides automatic recovery when this condition is detected. Under normal operating conditions, the output of the PWM Comparator will reset the Latch and discharge the internal Fault Timer capacitor on a cycle-by-cycle basis. Under operating conditions where the required power into the load is greater than that available from the source (Vin), the Ramp Input voltage (plus offset) will not reach the comparator threshold level (Pin 11), and the output of the PWM Comparator will remain low. If this condition persists for more that 600 s, the Fault Timer will active, discharging CSoft-Start and initiating a soft-start cycle. The power supply will operate in a skip cycle or hiccup mode until either the load power or source impedance is reduced. The minimum fault timeout is 200 s, which limits the useful switching frequency to a minimum of 5.0 kHz. Start/Run Comparator A bootstrap startup circuit is included to improve system efficiency when operating from a high input voltage. The output of the Start/Run Comparator controls the state of an external transistor. A typical application is shown in Figure 21. While CSoft-Start is charging, startup bias is supplied to VCC (Pin 14) from Vin through transistor Q2. When CSoft-Start reaches the 1.95 V clamp level, the Start-Run output switches low (VCC = 50 mV), turning off Q2. Operating bias is now derived from the auxiliary bootstrap winding of the transformer, and all drive power is efficiently converted down from Vin. The start time must be long enough for the power supply output to reach regulation. This will ensure that there is sufficient bias voltage at the auxiliary bootstrap winding for sustained operation. 1.95 V CSoft-Start tStart = = 1.95 CSoft-Start in F 1.0 A The Start/Run Comparator has 350 mV of hysteresis. The output off-state is clamped to VCC + 7.6 V by the internal zener and PNP transistor base-emitter junction. Drive Output and Drive Ground The MC34129 contains a single totem-pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to 1.0 A peak drive current and has a typical fall time of 30 ns with a 500 pF load. The totem-pole stage consists of an NPN transistor for turn-on drive and a high speed SCR for turn-off. The SCR design requires less average supply current (ICC) when compared to conventional switching control ICs that use an all NPN totem-pole. The SCR accomplishes this during turn-off of the MOSFET, by utilizing the gate charge as regenerative on-bias, whereas the conventional all transistor design requires continuous base current. Conversion efficiency in low power applications is greatly enhanced with this reduction of ICC. The SCR's low-state holding current (IH) is typically 225 A. An internal 225 k pull-down resistor is included to shunt the Drive Output off-state leakage to ground when the Undervoltage Lockout is active. A separate Drive Ground is provided to reduce the effects of switching transient noise imposed on the Ramp Input. This feature becomes particularly useful when the Ipk(max) clamp level is reduced. Figure 24 shows the proper implementation of the MC34129 with a current sensing power MOSFET. Undervoltage Lockout The Undervoltage Lockout comparator holds the Drive Output and CSoft-Start pins in the low state when VCC is less than 3.6 V. This ensures that the MC34129 is fully functional before the output stage is enabled and a soft-start cycle begins. A built-in hysteresis of 350 mV prevents erratic output behavior as VCC crosses the comparator threshold voltage. A 14.3 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the MOSFET gate from excessive drove voltage during system startup. An external 9.1 V zener is required when driving low threshold MOSFETs. Refer to Figure 21. The minimum operating voltage range of the IC is 4.2 V to 12 V. References The 1.25 V bandgap reference is trimmed to 2.0% tolerance at TA = 25C. It is intended to be used in conjunction with the Error Amp. The 2.50 V reference is derived from the 1.25 V reference by an internal op amp with a fixed gain of 2.0. It has an output tolerance of 5.0% at TA = 25C and its primary purpose is to supply charging current to the oscillator timing capacitor. For further information, please refer to AN976. 10 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 Figure 20. External Duty Cycle Clamp and Multi-Unit Synchronization 6 2.5V + - CSoft-Start 5.0V 5 RA RB 6 5 2 8 5.0k + - 5.0k + - 5.0k 1 4 R Q S MC1455 7 To Additional MC34129's R 5 4 OSC S Q 2 3 3 4 OSC 12 7 6 2.5V Figure 21. Bootstrap Startup Vin 13 Q2 + - + - + - + - + - 1.25V 14 9.1 V 8 + + - 9 10 11 1 C f= 1.44 (RA + 2RB)C RB Dmax = RA + 2RB The external 9.1 V zener is required when driving low threshold MOSFETs. Figure 22. Discrete Step Reduction of Clamp Level Vin 8 1.25V + 275mV 9 + + Figure 23. Adjustable Reduction of Clamp Level Vin 8 1.25V + 275mV 9 + + - - 10 11 - - 10 11 R1 R2 Q1 Q1 R Q S 2 3 3 D1 D2 RS 120A RS 1 S R Q 2 1 Ipk(max) = 1.675 - (VF(D1) + VF(D2)) RS If: 1.25 V 1.0 mA R1 + R2 Then: Ipk(max) 1.25 R2 +1 R1 RS - 0.275 MOTOROLA ANALOG IC DEVICE DATA 11 MC34129 MC33129 Figure 24. Current Sensing Power MOSFET Vin 8 1.25V 9 VRS RS Ipk rDS(on) rDM(on) + rS Vin Figure 25. Current Waveform Spike Suppression + - 10 D 11 1 G 2 3 RS 1/4W Control Circuitry Ground: To Pin 7 M K If: SENSEFET = MTP10N10M RS = 200 Then: VRS 0.075 Ipk SENSEFET 1 2 S 3 R C Power Ground: To Input Source Return RS Q1 The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. Figure 26. MOSFET Parasitic Oscillations Figure 27. Bipolar Transistor Drive IB Vin Vin + 0 - t Base Charge Removal C1 1 1 Rg Q1 2 2 3 RS 3 Q1 RS Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. The totem-pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. 12 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 Figure 28. Non-Isolated 725 mW Flyback Regulator 220k + - 13 + 2.2k 2N5551 50 Vin = 20V to 48V 14 12 + - 1N958A 0.1 7 + - + - 6 2.5 V + - 8 1.25V 9 + - 10 500pF 11 24k R 5 OSC 470pF 4 128kHz Sync 3 S Q 2 1 1N4148 + 10 T1 + 36k R2 100 Gnd + 100 1N5819 5V/125mA 12k R1 -5V/20mA 1N5819 MTP 2N20L 10 T1: Coilcraft #G6807-A Primary = 90T #28 AWG Secondary 5V = 26T #30 AW Gap = 0.05 n, for Lp of 600 H Core = Ferroxcube 813E187-3C8 Bobbin = Ferroxcube E187PCB1-8 Test Line Regulation 5.0 V Load Regulation 5.0 V Output Ripple 5.0 V Efficiency Conditions Vin = 20 V to 40 V, Iout 5.0 V = 125 mA, Iout -5.0 V = 20 mA Vin = 30 V, Iout 5.0 V = 0 mA to 150 mA, Iout -5.0 V = 20 mA Vin = 30 V, Iout 5.0 V = 125 mA, Iout -5.0 V = 20 mA Vin = 30 V, Iout 5.0 V = 125 mA, Iout -5.0 V = 20 mA Results = 1.0 mV = 2.0 mV 150 mVpp 77% Vout = 1.25 R2 +1 R1 MOTOROLA ANALOG IC DEVICE DATA 13 MC34129 MC33129 Figure 29. Isolated 2.0 W Flyback Regulator 220k + - 12 14 + - 0.1 7 + - + - 1.25V 9 + - 13 2.2k 2N5551 1N5819 1N5819 + 8 0.1 140k 330 2 180 pF T1 + 100 Vin = 20V to 48V 1N5819 5V/380mA + 100 Gnd + 100 6 2.5V + - 10 11 20k 1N5819 -5V/20mA 24k R 5 OSC 470pF 128kHz Sync 0.1 1 2.7k 6 10k 4 2 5 MOC5007 4 S Q 1 2 3 MTP 2N20 100pF 100 T1: Primary = 35T #32 AWG Feedback = 12T #32 AWG Secondary 5 V = 7T #32 AWG Gap = 0.004, for Lp of 180 H Core = Ferroxcube 813E187-3C8 Bobbin = Ferroxcube E187PCB1-8 Test Line Regulation 5.0 V Load Regulation 5.0 V Output Ripple 5.0 V Efficiency Conditions Vin = 20 V to 40 V, Iout 5.0 V = 380 mA, Iout -5.0 V = 20 mA Vin = 30 V, Iout 5.0 V = 100 mA to 380 mA, Iout -5.0 V = 20 mA Vin = 30 V, Iout 5.0 V = 380 mA, Iout -5.0 V = 20 mA Vin = 30 V, Iout 5.0 V = 380 mA, Iout -5.0 V = 20 mA Results = 1.0 mV = 15 mV 150 mVpp 73% 14 MOTOROLA ANALOG IC DEVICE DATA MC34129 MC33129 Figure 30. Isolated 3.0 W Flyback Regulator with Secondary Side Sensing Vin = 12V + - 13 14 100 1N5821 L1 5/60mA 3.9k + 12 51 + 1/2 0.1 7 6 2.5V + - + - + - 470 8 1.25V 9 + - 4N26 0.1 3.9k 100 D 10 11 TL431A MTP10N10M S Return 2.2k 15k R 5 OSC 4 0.002 S Q 1 2 3 G M K 1/2 4N26 T1: Primary = 22T #18 AWG Secondary = 22T #18 AWG Lp = 50 H Core = Ferroxcube 2616PA100-3C8 L1: Bobbin = Ferroxcube 2616F1D Coilcraft Z7156, 15 H 510 0.001 Test Line Regulation Load Regulation Output Ripple Efficiency Conditions Vin = 8.0 V to 12 V, Iout 600 mA Vin = 12 V, Iout = 100 mA to 600 mA Vin = 12 V, Iout = 600 mA Vin = 12 V, Iout = 600 mA 200 Results = 1.0 mV = 8.0 mV 20 mVpp 81% An economical method of achieving secondary sensing is to combine the TL431A with a 4N26 optocoupler. MOTOROLA ANALOG IC DEVICE DATA 15 MC34129 MC33129 OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE L NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01 14 8 B 1 7 A F C N H G D SEATING PLANE L J K M -A- 14 8 D SUFFIX PLASTIC PACKAGE CASE 751A-03 (SO-14) ISSUE F -B- 1 7 P 7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 1 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 16 *MC34129/D* MOTOROLA ANALOG IC DEVICE DATA MC34129/D |
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